1. Field of the Invention
The invention relates to a semiconductor structure and a battery protection circuit having the same, and more particularly, to a low voltage complementary metal oxide semiconductor (CMOS) structure for a battery protection circuit using tri-well or buried layer technique and the battery protection circuit using such structure.
2. Description of Related Prior Art
The operation voltage for a cell lithium-ion battery pack is between 2.4 to 4.2 volts. The protection circuit of the lithium-ion battery pack uses a voltage detection circuit to provide the detection state of the voltage of each battery. While charging the lithium-ion battery pack, an external source voltage supplied to the lithium battery pack is switched off when the voltage is over 4.3 volts to avoid overcharge, so as to prevent explosion of the lithium-ion battery pack. When the operation voltage is lower than 2.3 volts, the discharging operation of the lithium-ion battery pack is switched off to avoid over-discharge that damages the lithium-ion battery pack and reduces the lifetime thereof.
The above voltage detection circuit can be referred to U.S. Pat. No. 6,225,779, xe2x80x9cPower Supply Monitoring Integrated Circuit Device for Individually Monitoring Voltage of Cellsxe2x80x9d or U.S. Pat. No. 6,285,165 xe2x80x9cSecondary Battery Protection Circuitxe2x80x9d.
The battery protection circuit further includes an excess current protection circuit and a short current protection circuit that switches off the load connection of the lithium-ion battery pack under abnormal condition of the operation current, and resumes to normal operation after the abnormal condition is released.
However, while using the CMOS process to realize the multi-cells lithium-ion battery protection circuit, being affected by the substrate bias, the operation voltage of the circuit is higher than the breakdown voltage of the low voltage CMOS process. Thus, the battery protection circuit for the battery can not be realized using the low voltage CMOS process.
The present invention provides a CMOS structure and a battery protection circuit including the same. The CMOS structure can be realized by tri-well or buried layer technique, such that the battery protection circuit of each battery can be operated with relatively low voltage without being affected by substrate bias. In addition, the chip area and cost are effectively reduced, and the design can be simplified.
The present invention further provides a CMOS structure and a battery protection circuit including such CMOS structure that has the function of isolating substrate noise.
The CMOS structure and the battery protection circuit including such CMOS structure provided by the present invention are operative to prevent the occurrence of an unbalanced condition in the battery to be protected.
The CMOS structure for a battery protection circuit comprises a P-type substrate, an N-type metal oxide semiconductor (NMOS) transistor and a P-type metal oxide semiconductor (PMOS) transistor. The P-type substrate includes a P-well and an N-well adjacent to each other, and the P-well has an N-type buried layer to isolate it from the substrate. The NMOS transistor is formed in the P-well, while the PMOS transistor is formed in the N-well. The NMOS transistor includes a gate connected to an input terminal, a source coupled to a first voltage level, and a drain coupled to an output terminal. The PMOS transistor has a gate coupled to the input terminal, a source coupled to a second voltage level, and a drain coupled to the output terminal, where the first voltage level is lower than the second voltage level.
The present invention further provides a CMOS structure for a battery protection circuit including an N-type substrate, an NMOS transistor and a PMOS transistor. The N-type substrate has a P-well and an N-well adjacent thereto, where the N-well includes a P-type buried layer to isolate it from the N-type substrate. The NMOS transistor is formed in the P-well, while the PMOS transistor is formed in the N-well. The NMOS transistor includes a gate coupled to an input terminal, a source coupled to a first voltage level, and a drain coupled to an output terminal. The PMOS transistor includes a gate coupled to the input terminal, a source coupled to a second voltage level, and a drain coupled to the output terminal, where the first voltage level is lower than the second voltage level.
The present invention also provides a CMOS structure for a battery protection circuit including a P-type substrate, an NMOS transistor and a PMOS transistor. A deep N-well is formed in the P-type substrate, and a P-well isolated from the P-type substrate is formed in the deep N-well. An NMOS transistor is formed in the P-well. The NMOS transistor includes a gate coupled to an input terminal, a source coupled to a first voltage level, and a drain coupled to an output terminal. A PMOS transistor is formed in the deep N-well and includes a gate coupled to the input terminal, a source coupled to a second voltage level, and a drain coupled to the output terminal.
The present invention further provides a CMOS structure for a battery protection circuit, including an N-type substrate, an NMOS transistor and a PMOS transistor. The N-type substrate includes a deep P-well formed in the N-type substrate, and an N-well is formed in the deep P-well isolated from the substrate. The NMOS transistor is formed in the deep P-well and comprises a gate coupled to an input terminal, a source coupled to a first voltage level, and a drain coupled to an output terminal. The PMOS transistor is formed in the N-well and includes a gate coupled to the input terminal, a source coupled to a second voltage level, and a drain coupled to the output terminal.
The present invention further provides a battery protection circuit to detect battery voltage and current of a battery pack, so as to protect the battery pack. The battery protection circuit includes a multi-overcharging and over-discharging units to monitor the voltage level of each battery of the multi-cell battery pack. The overcharging and over-discharging protection units are formed of a CMOS structure. The battery protection circuit further comprises a level shift circuit and a logic and delay circuit. The level shift circuit is coupled to the overcharging and the over-discharging units to adjust the potentials of multi-channel comparison signals output from the overcharging and over-discharging circuits. The logic and delay circuit is coupled to the level shift circuit to receive the adjusted comparison signals and controls the external switches. A first signal and a second signal are output in response to the comparison signals. If the potential of the first signal is logic 1, it indicates that the battery pack is over-discharging, and when the potential of the second signal is logic 1, the battery pack is overcharging.
The CMOS structure of the above overcharging and over-discharging units includes various types of structures.
In addition, an excess current protection unit, a short circuit protection unit and a voltage regulator are also applied to above battery protection circuit. The excess current protection unit and the short current protection unit provide the protection by switching off the load of the lithium-ion battery pack when the current of the battery pack is under an abnormal operation condition. A level shift circuit is used to adjust the potentials of a set of comparison signals. A logic and delay circuit is also included and coupled to the level shift circuit to receive the comparison signals after being adjusted. The logic and delay circuit further outputs a signal to an external switch after integrating the detection results of the over-discharging unit. The voltage regulator provides source voltage to the excess current protection unit and the short circuit current protection unit.
The CMOS structure of the above excess current protection unit and short-circuit current protection unit include various types of structures as mentioned above.
In the above battery protection circuit, the overcharging and over-discharging units further comprise a first comparator, a second comparator, and a bandgap reference voltage-generating unit which is coupled to the first and second comparators. Wherein, the first comparator is coupled to a voltage level that is to be monitored, and outputs a first signal after comparing the voltage level with a reference voltage, provided by the bandgap reference voltage-generating unit. The second comparator is coupled to the voltage level to be monitored by the first comparator and outputs the second signal after comparing with a reference voltage provided by the bandgap reference voltage-generating unit.
The battery protection circuit of the present invention, that uses a bandgap reference voltage-generating unit to generate the reference voltage and the comparator, requires a relatively low voltage and current to reduce power consumption. In addition, the excess current protection unit, the short circuit protection unit and the voltage regulator avoid any unbalanced condition generated by the battery pack during operation of the circuit protection circuit.
The battery protection circuit using the tri-well or buried layer structure is also operative to isolate the substrate noise.